Handheld consumer electronics require packaging technologies which are able to provide more compact sizes, higher performance, and/or low costs. These market requirements motivate the transition of the die placement from side by side to die stacking. Also, these requirements encourage the switching of interconnection technologies from wire bonding to vertical interconnections using Through Silicon Vias (TSVs). FIG. 1A is an image 100a showing wirebond stacking. FIG. 1B is an image 100b showing through silicon via (TSV) stacking.
TSV technology has been considered as a promising platform for 3D stacking as well 2.5D interposer to accommodate high input/output (I/O) and smaller form factor. However, this technology may still be considered as a high cost process due to relative expensive front-end process such as dual damascene, deep reactive-ion etching (DRIE) etching, chemical vapor deposition (CVD) etc.
FIG. 2 is a schematic 200 showing process flow of through silicon via (TSV) die stacking. “FEOL” refers to Front End of Line and “BEOL” refers to Back End of Line. “C4 bump formation” refers to controlled collapse chip connection bump formation or flip chip bump formation. The process flow may include 3 main processes: fab wafer process, post fab wafer process, and assembly and packaging process. The conventional die stacking process using TSV includes Back End of Line (BEOL) processing methods such as deep reactive-ion etching (DRIE), chemical vapor deposition (CVD) and plating, as well as packaging methods such as bumping, backgrinding, Temporary Bonding Debonding (TBDB), and thermal compression bonding.